Optical data links between computers are becoming more popular as optical technologies mature. However, there is a noticeable absence of “intelligence” that is included in existing optoelectronic devices that deal with data transmission and reception at the physical layer. Typically, existing data links operate at a nominal clock rate of typically 1 GigaHertz (GHz) with a nominal Bit Error Rate (BER) of typically 10^-12, i.e., one bit error per 10^12 bits transmitted. One example of such a requirement specification is described in the standard “High Performance Parallel Interface” (HIPPI) in the document “Information Technology—High-Performance Parallel Interface—6400 Mbit/s Optical Specification (HIPPI-6400-OPT), Working Draft T11.1/Project 1249-D/Rev 1.6”, available from the National Committee for Information Technology Standardization. Another relevant document is “Information Technology—High-Performance Parallel Interface—Mechanical, Electrical and Signaling Protocol Specification (HIPPI-PH)”, available from the National Committee for Information Technology Standardization. This standard specifies that receivers need not detect errors, and that retransmissions can be requested by an upper-layer protocol.
Other examples of optical data links are described in the IEEE Journal of Selected Topics in Quantum Electronics (JSTQE), which published a special issue on “Smart Photonic Components, Interconnects and Processing”, Vol. 5, No. 2, (which was printed sometime after Apr. 21, 1999), which is hereby incorporated by reference. The special issue contains papers describing integrated optoelectronic integrated circuits for several applications.
A parallel optical datalink is described by A. Neyer et al, “Plastic-Optical-Fiber-based parallel Optical Interconnects”, JSTEQ, pg. 193. They describe a parallel 8×8 fiber datalink between two integrated circuits. A free-space optical datalink is described by D. A. Louderback et al, “Modulation and Free-Space Link Characteristics of Monolithically Integrated vertical cavity lasers and Photodetectors with Microlenses”, JSTQE pg. 157. They describe the process on integrating Vertical cavity Lasers and photodetectors onto CMOS integrated circuits. A parallel link is described by H. Kosada “Smart Integration and Packaging of 2-D VCSEL's for High Speed Parallel Links”, JSTQE pg. 184. This paper describes integration and packaging of 2 dimensional arrays of Vertical Cavity Surface Emitting Lasers (VCSELs) and photodetectors. An optoelectronic crossbar switch is described by Walker et. al., “Design and Construction of an Optoelectronic Crossbar Switch Containing a Terabit per second Free-Space Optical Interconnect”, JSTQE pg. 236. This paper describes integration of detectors and optical modulators onto a silicon substrate. An optoelectronic computing system is described by McArdle et al, “Optoelectronic Parallel Computer Using Optically Interconnected Pipelined Processing Arrays”, JSTQE pg. 250. The devices which are optically interconnected perform logical data processing on the data that passes through them. An optical switch is described by Krishnamoorthy et al, “The AMEBA Switch: An Optoelectronic Switch for Multiprocessor Networking Using Dense-WDM”, JSTQE pg. 261. The switch uses multiple quantum well diodes which have been flip chip bonded onto a CMOS substrate; these diodes can act as both detectors and modulators of externally supplied laser beams. This switch is intended to interconnect multiple processors. The above are hereby incorporated by reference.
The aforementioned papers represent the state-of-the-art in “smart photonic components”, i.e., components which merge processing with optical transmission technologies. Such technologies include VCSELs and Photodetector Arrays (PDs) which can be flip chip bonded onto CMOS integrated circuits, as described in D. A. Louderback et al, JSTQE pg. 157. One common drawback with all of the aforementioned papers is the lack of error control processing at the lowest level of the protocol hierarchy, i.e., in the CMOS integrated circuits closest to the optical sources and detectors. The prevailing view of the integrated optoelectronics community is that any error control is not required at the lowest levels of the communication hierarchy. The prevailing view of the optical datalink community (i.e., HIPPI) is that any “significant” level of error control is not required at the lowest levels of the communication hierarchy, where a significant level of error control is defined as a requirement of a Bit Error Rate of between 10^-20 and 10^-30. These BERs are approx. one billionth of the raw BERs specified by standards such as HIPPI. Typically, all significant error control processing is migrated up to a higher level of the protocol stack, where it may be performed by software in an “off-line” manner, well after the data has been received.
Schemes used to encode data to allow for the subsequent detection and correction of bit errors are well known and understood. S. Lin and D. J. Costello, “Error Control Coding”, Prentice Hall 1983, the contents of which are hereby incorporated by reference describes a variety of such schemes (hereafter “Lin & Costello”). These are typically used for general reliability in the transfer and storage of data and to communicate data across an imperfect channel that may introduce errors into transmitted data.
For example, parity and cyclic redundancy checks (“CRC”s) are often used for error detection (“ED”). Alternatively, forward error correction (“FEC”) schemes may be used for the detection and correction of errors within received data. Known (n,k) FEC codes use a n bit vector to encode k actual data bits, while being to able to detect and correct at least some errors within the k data bits.
Most existing FEC schemes, however, are ill suited to the detection and correction of errors at very high speeds. Thus, such schemes are typically not used in optical communications systems, and particularly not at lower layers of any protocols used in optical systems. Primarily, this is because the existing schemes are computationally complex and can therefore not be executed at extremely high speeds typical of such systems. Present hardware implementations of FEC encoders and decoders for such schemes can require large numbers of transistors.
Moreover, conventional wisdom further suggests that use of such FEC codes detracts from available bandwidth across a data link. That is, as error correction/detection codes are added, a higher percentage of nominally available bandwidth is used for overhead, rather than for actual data. As such, conventional error detection schemes used with optical systems typically strive to be simple, adding minimal overhead.
Recent research, as for example detailed in Neifeil and Kostuk, Error Correction For Free Space Optical Interconnects: Space-Time Resource Optimization, Applied Optics, Volume 37, No. 2, January 1998 however, has shown that it may be possible to increase the effective bandwidth of an optical or similar link, by operating the link at a rate higher than its rated bandwidth and compensating for newly introduced errors using Reed-Solomon (“RS”) FEC codes. Specifically, as will be appreciated by those of ordinary skill in the art, the rated data rate of a typical link is designed so that the link may be used up to a rated data rate with a nominal raw bit error rate (BER), in the absence of any error correction. Typically, as the link is operated at a higher data rate, the raw BER also increases. So, properly chosen FEC codes could compensate for the increased raw BER. At present, however, operation of high speed links at increased speeds is only a theoretical possibility as the suggested FEC schemes cannot be processed at these increased speeds required by optical links.
In particular, Neifeld and Kostuck demonstrated theoretically data rate improvements by a factor of 2 to 8, although some of the improvement was due to the use of a larger number of optical sources and detectors. If the number of transmitters and receivers is kept fixed, to isolate the effect of the Reed-Solomon code only, the increase in the data rate will be strictly less than 2 and 8 respectively. A hardware implementation of a RS code is described in M. A. Neifeld, and S. K. Sridharan, Parallel Error Correction using Spectral Reed-Solomon Code, Journal of Optical Communications, 17, pp. 525-531, 1997. They demonstrate that 1 cm×1 cm of silicon area is required to process a 77 Gigabit per second (Gbps) datalink, yielding a BER of 10^-6 on the processed data stream.
Therefore, to process a 1 Terabit per second (Tbps) data link using the technique of Neifeild and Kostuck will require 13 separate ICs (1 Tbps/77 Gbps=13). To process a 10 Terabit per second data link will require 130 of these FEC decoder ICs. It is physically impossible to get 10 Terabits of data off of a photodetector array integrated circuit, and into 130 ICs to perform error correction, due to physical constraints on the packaging of the integrated circuit. Integrated circuit packaging constraints are discussed in the “Microelectronics Packaging Handbook”, Ed. R. Tummala and E. Rymaszewski, Van Nostrand Reinhold, New York, which is hereby incorporated by reference. Current integrated circuit packages are restricted to have several hundred or thousand electrical I/O pins, which can be clocked at typically less than 1 GHz each, for a total electrical Input/Output bandwidth of less than a few Terabits per second (Tbps). Furthermore, even if it was possible to remove 10 Tbps of data from a photodetector array integrated circuit and process this data over a large number of electronic processing integrated circuits, the BER on the processed data stream will be approx. 10^-6, which is very high.
Conventional FECs such as RS codes typically also require a large amount of time to decode. Attempts to speed up the FEC process have had limited success. Gibbs et. al. U.S. Pat. No. 5,383,204 describes one approach to speed up the Reed Solomon FEC, and illustrates how to reduce the number of clock steps to decode the RS code from approx. 2,300 to 1,100. In many applications such as high speed computer communications, a delay of 1,100 steps would be intolerable.
The existing ED and FEC schemes are inadequate for the next generation of very high capacity optical datalinks, using for example medical Fiber Image Guides to transports hundreds or thousands of optical bits. Fiber Image Guides are described in Yao Li U.S. Pat. No. 5,579,426, “Fiber Image Guide Based Bit-Parallel Computer Interconnect”. Consider an optical data link where 1,024 bits of data arrive at every clock tick, with a 10 GHz clock rate, for a total data rate of 10 Terabits per second. Such data links do not exist in real systems. This data rate is several orders of magnitude beyond the data rates of existing optical interconnections.
Furthermore, conventional wisdom suggests that use of Error Detection codes and retransmissions detracts from available bandwidth across a data link.
Accordingly, a new transmission method using relatively computationally simple coding schemes is desirable, that may be used in optical and similar systems, in order to increase the effective bandwidth available on a given link, or to decrease the effective BER on the processed data, or preferably both.